1. Field of the Invention
The invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the invention relates to a vertical channel transistor array and a manufacturing method thereof.
2. Description of Related Art
With development of powerful microprocessors, software is more capable of programming and calculating an increasing amount of data. Therefore, the fabrication of memories is essential to the semiconductor industry. A dynamic random access memory (DRAM) is a volatile memory formed by a plurality of memory cells. Each of the memory cells is mainly included of a transistor and a capacitor, and all of the memory cells are electrically connected to one another through a word line (WL) and a bit line (BL).
As science and technology advance, a length of a channel region in the transistors of the DRAM is decreased together with the requirement for device size reduction, and thereby operation speed of the device can be increased. Nonetheless, in such case, a short channel effect is likely to occur in the transistors, and an On current may be decreased.
Hence, according to the related art, a horizontal transistor is changed to a vertical transistor. As proposed in U.S. Pat. No. 7,355,230, the vertical transistors are formed in trenches in the DRAM, and embedded bit lines and embedded word lines are formed as well.
Yet, with miniaturization of the device, the distance between the adjacent embedded bit lines is decreased. As such, during operation of the DRAM, current leakage is prone to occur at bottoms and terminals of the embedded bit lines, which further deteriorates device performance.